More and more peripheral devices are developed to operate in coordination with computer systems. Usually, the peripheral device asserts an interrupt signal to request the central processing unit (CPU) of the computer system to perform an interrupt service. Please refer to FIG. 1, which is a functional block diagram illustrating conventional interrupt control means of a computer system. In response to an external interrupt signal asserted by a peripheral device 11 to a programmable interrupt controller (PIC) 121 in the south bridge chip 12, the PIC 121 informs the CPU 13 of the assertion of the external interrupt signal via an interrupt pin (INTR pin). When realizing the interrupt signal assertion, the CPU 13 reads an interrupt vector associated with the external interrupt signal from the PIC 121. According to the interrupt vector, the CPU 13 accesses a service routine from the system memory 10 via the north bridge chip 14 so as to execute the interrupt service. Different interrupt vectors relate to different service routines stored at different addresses in the system memory 10. In the aforementioned prior art, which is so-called as a “PIC mode”, the PIC 121 informs the CPU 13 of the interrupt signal assertion via the INTR pin, and then the CPU 13 has to activate an additional reading procedure to obtain the interrupt vector from the PIC 121, which makes the interrupt control complicated.